Several three-dimensional integrated circuit memories utilize vertically-stacked layers of memory cells on a single integrated circuit. See, for example, U.S. Pat. Nos. 6,034,882 and 6,420,215 and U.S. patent application No. US2002/0028541, which are assigned to the assignee of the present invention. When the numerous layers of memory cells are sequentially fabricated onto an integrated circuit device using standard high-volume manufacturing processes, the resulting numerous layers of cells may not be perfectly identical. For example, there may be “random” differences (i.e., differences that fluctuate from device to device and from manufacturing lot to manufacturing lot) among the layers on a three-dimensional memory chip. Often, it is found that random differences among layers of the same chip are caused by normal, random fluctuations of the high-volume manufacturing process. “Systematic” differences (i.e., differences that are generally observed to occur on many or perhaps most of the manufactured units) may also appear among layers of the same chip. Systematic differences may arise due to different designs of the different layers, as, for example, in U.S. Pat. Nos. 6,034,882 and 6,420,215, where even-numbered layers have a unidirectional current-flow element in one orientation, while odd-numbered layers have a unidirectional current-flow element in an opposite orientation. Other causes of systematic differences among layers are possible. For example, systematic differences may be caused by different manufacturing machines used on different layers, differences between photomasks (e.g., slightly different linewidths) used to fabricate different layers, cumulative per-layer effects (e.g., total-time-at-temperature) leading to a gradient of differences between the sequentially-processed layers on a chip, and different layer-to-layer misalignments.
Random and/or systematic differences between layers of memory cells on the same integrated circuit can give rise to undesirable consequences. For example, different layers may have different “writing thresholds,” meaning that for a certain individual unit, the optimum conditions for writing memory cells in layer A may be different than the optimum conditions for writing memory cells in layer B. Different layers of memory cells may operate slightly differently in read operations as well. That is, for a certain individual unit, the optimum conditions for reading memory cells in layer C may be different than the optimum conditions for reading memory cells in layer D. In a conventional design, the same writing and reading conditions are used for all memory cell layers. Due to random and/or systematic differences among memory cell layers, this rigid application of the same write and read conditions for all layers means that some layers are written and read at less than optimal conditions.